From f8daf08aba1f09c3024a70d3426891112d1662a2 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 12 Aug 2026 21:35:21 +0800
Subject: [RISCV] Consolidate instruction behavior in RISCVInstrInfo

---
 backend/include/rcc/CodeGen/TargetInstrInfo.h | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

(limited to 'backend/include/rcc/CodeGen/TargetInstrInfo.h')

diff --git a/backend/include/rcc/CodeGen/TargetInstrInfo.h b/backend/include/rcc/CodeGen/TargetInstrInfo.h
index d9f0906..34752c5 100644
--- a/backend/include/rcc/CodeGen/TargetInstrInfo.h
+++ b/backend/include/rcc/CodeGen/TargetInstrInfo.h
@@ -3,8 +3,11 @@
 #ifndef RCC_CODEGEN_TARGETINSTRINFO_H
 #define RCC_CODEGEN_TARGETINSTRINFO_H
 
+#include "rcc/CodeGen/MachineIRTypes.h"
+#include "rcc/CodeGen/Register.h"
 #include "rcc/Support/Error.h"
 
+#include <cstddef>
 #include <cstdint>
 #include <optional>
 
@@ -40,8 +43,25 @@ public:
                       MachineBasicBlock &NewTarget, MachineFunction &Function,
                       const TargetDescription &Target) const = 0;
   [[nodiscard]] virtual Expected<MachineInstr *>
-  insertUnconditionalBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock,
-                            MachineFunction &Function, const TargetDescription &Target) const = 0;
+  insertBranch(MachineBasicBlock &Block, MachineBasicBlock &TargetBlock, MachineFunction &Function,
+               const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<bool> isFallthroughEdge(const MachineBasicBlock &From,
+                                                         const MachineBasicBlock &To,
+                                                         const MachineFunction &Function,
+                                                         const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<void> validateCopy(Register Destination,
+                                                    SubRegIndex DestinationSubReg, Register Source,
+                                                    SubRegIndex SourceSubReg,
+                                                    const MachineFunction &Function,
+                                                    const TargetDescription &Target) const = 0;
+
+  [[nodiscard]] virtual Expected<bool> tryConvertToThreeAddress(MachineInstr &, std::size_t,
+                                                                std::size_t, MachineFunction &,
+                                                                const TargetDescription &) const {
+    return false;
+  }
 
   [[nodiscard]] virtual Expected<std::uint32_t>
   instructionSize(const MachineInstr &Instruction, const MachineFunction &Function,
-- 
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