From 3a57627e59ba18b6f9f9aae7bb60c390c0d3575a Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sun, 9 Aug 2026 22:05:14 +0800 Subject: [MC] Implement RV64GC object emission --- backend/include/rcc/Target/RISCV/RISCVAsmBackend.h | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 backend/include/rcc/Target/RISCV/RISCVAsmBackend.h (limited to 'backend/include/rcc/Target/RISCV/RISCVAsmBackend.h') diff --git a/backend/include/rcc/Target/RISCV/RISCVAsmBackend.h b/backend/include/rcc/Target/RISCV/RISCVAsmBackend.h new file mode 100644 index 0000000..11dcb77 --- /dev/null +++ b/backend/include/rcc/Target/RISCV/RISCVAsmBackend.h @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#ifndef RCC_TARGET_RISCV_RISCVASMBACKEND_H +#define RCC_TARGET_RISCV_RISCVASMBACKEND_H + +#include "rcc/MC/MCAsmBackend.h" + +namespace rcc::riscv { + +class RISCVAsmBackend final : public mc::MCAsmBackend { +public: + [[nodiscard]] Expected fixupKindInfo(mc::MCFixupKind Kind) const override; + [[nodiscard]] Expected applyFixup(mc::MCFixupKind Kind, std::span Data, + std::uint64_t Offset, std::int64_t Value) const override; + [[nodiscard]] Expected relocationType(const mc::MCFixup &Fixup, + const mc::MCValue &Value) const override; + [[nodiscard]] Expected> + relocationsForFixup(const mc::MCFixup &Fixup, const mc::MCValue &Value) const override; + + [[nodiscard]] bool mayNeedRelaxation(const mc::MCInst &Instruction) const noexcept override; + [[nodiscard]] Expected fixupNeedsRelaxation(const mc::MCFixup &Fixup, + std::int64_t Value) const override; + [[nodiscard]] Expected relaxInstruction(const mc::MCInst &Instruction) const override; + + [[nodiscard]] std::uint32_t objectFlags() const noexcept override; +}; + +} // namespace rcc::riscv + +#endif // RCC_TARGET_RISCV_RISCVASMBACKEND_H -- cgit v1.2.3