From e5fdceb9b869f010a2a75638fd38aaf1867f3008 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 04:40:17 +0800
Subject: [CodeGen] Complete register allocation infrastructure

---
 backend/include/rcc/Target/RISCV/RISCVCodeGen.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'backend/include/rcc/Target/RISCV/RISCVCodeGen.h')

diff --git a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
index 4db60f7..403bb2d 100644
--- a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
+++ b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
@@ -4,6 +4,7 @@
 #define RCC_TARGET_RISCV_RISCVCODEGEN_H
 
 #include "rcc/CodeGen/TargetCodeGen.h"
+#include "rcc/CodeGen/TargetRegisterAllocationInfo.h"
 
 namespace rcc::riscv {
 
@@ -11,6 +12,7 @@ namespace rcc::riscv {
 [[nodiscard]] const TargetRegisterBankInfo &registerBankInfo() noexcept;
 [[nodiscard]] const TargetInstructionSelector &instructionSelector() noexcept;
 [[nodiscard]] const TargetSSAInfo &ssaInfo() noexcept;
+[[nodiscard]] const TargetRegisterAllocationInfo &registerAllocationInfo() noexcept;
 
 } // namespace rcc::riscv
 
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