From 3a57627e59ba18b6f9f9aae7bb60c390c0d3575a Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sun, 9 Aug 2026 22:05:14 +0800 Subject: [MC] Implement RV64GC object emission --- .../include/rcc/Target/RISCV/RISCVMCCodeEmitter.h | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 backend/include/rcc/Target/RISCV/RISCVMCCodeEmitter.h (limited to 'backend/include/rcc/Target/RISCV/RISCVMCCodeEmitter.h') diff --git a/backend/include/rcc/Target/RISCV/RISCVMCCodeEmitter.h b/backend/include/rcc/Target/RISCV/RISCVMCCodeEmitter.h new file mode 100644 index 0000000..700cdc2 --- /dev/null +++ b/backend/include/rcc/Target/RISCV/RISCVMCCodeEmitter.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#ifndef RCC_TARGET_RISCV_RISCVMCCODEEMITTER_H +#define RCC_TARGET_RISCV_RISCVMCCODEEMITTER_H + +#include "rcc/CodeGen/TargetDescription.h" +#include "rcc/MC/MCCodeEmitter.h" + +namespace rcc::riscv { + +class RISCVMCCodeEmitter final : public mc::MCCodeEmitter { +public: + explicit RISCVMCCodeEmitter(const TargetDescription &Target) noexcept : Target(&Target) {} + + [[nodiscard]] Expected + encodeInstruction(const mc::MCInst &Instruction) const override; + +private: + const TargetDescription *Target; +}; + +} // namespace rcc::riscv + +#endif // RCC_TARGET_RISCV_RISCVMCCODEEMITTER_H -- cgit v1.2.3