From 81afb6570000472c182e5b1f540f69382602aaad Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Mon, 24 Aug 2026 17:30:29 +0800 Subject: [RISCV] Match LLVM emergency spill layout --- backend/include/rcc/Target/RISCV/RISCVPipeline.h | 1 + 1 file changed, 1 insertion(+) (limited to 'backend/include/rcc/Target/RISCV/RISCVPipeline.h') diff --git a/backend/include/rcc/Target/RISCV/RISCVPipeline.h b/backend/include/rcc/Target/RISCV/RISCVPipeline.h index 21a4461..50a6a68 100644 --- a/backend/include/rcc/Target/RISCV/RISCVPipeline.h +++ b/backend/include/rcc/Target/RISCV/RISCVPipeline.h @@ -25,6 +25,7 @@ struct RISCVPipelineOptions final { bool UseTargetCopyInstructions = false; GlobalISelAbortMode GlobalISelAbort = GlobalISelAbortMode::Enable; bool DebugMachineScheduler = false; + bool DebugPrologueEpilogue = false; }; [[nodiscard]] Expected addCanonicalPipeline(MachineFunctionPassManager &Pipeline, -- cgit v1.2.3