From e16de95dce32f077361577377d5c52fc4ad78339 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Fri, 7 Aug 2026 02:15:09 +0800
Subject: [RISCV] Add generated RV64GC register description

Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling.
---
 backend/include/rcc/Target/RISCV/RISCVTarget.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 backend/include/rcc/Target/RISCV/RISCVTarget.h

(limited to 'backend/include/rcc/Target/RISCV/RISCVTarget.h')

diff --git a/backend/include/rcc/Target/RISCV/RISCVTarget.h b/backend/include/rcc/Target/RISCV/RISCVTarget.h
new file mode 100644
index 0000000..948e22d
--- /dev/null
+++ b/backend/include/rcc/Target/RISCV/RISCVTarget.h
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#ifndef RCC_TARGET_RISCV_RISCVTARGET_H
+#define RCC_TARGET_RISCV_RISCVTARGET_H
+
+#include "rcc/CodeGen/TargetMIRTextInfo.h"
+#include "rcc/CodeGen/TargetRegisterInfo.h"
+#include "rcc/Support/Error.h"
+#include "rcc/Target/RISCV/RISCVRegisters.h"
+
+#include <cstdint>
+#include <memory>
+
+namespace rcc::riscv {
+
+[[nodiscard]] Expected<PhysicalRegister> physicalRegister(PhysicalRegisterID ID);
+[[nodiscard]] Expected<TargetRegisterInfo> createRegisterInfo();
+[[nodiscard]] Expected<TargetMIRTextInfo> createMIRTextInfo();
+[[nodiscard]] std::shared_ptr<const RegisterMask> createCallPreservedMask();
+
+} // namespace rcc::riscv
+
+#endif // RCC_TARGET_RISCV_RISCVTARGET_H
-- 
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