From 71988f9818677df0d90b19d4bb770ac8a6116e62 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Tue, 25 Aug 2026 02:21:25 +0800
Subject: [CodeGen] Implement RISC-V machine outlining

---
 backend/include/rcc/Target/RISCV/RISCVPipeline.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'backend/include/rcc/Target/RISCV')

diff --git a/backend/include/rcc/Target/RISCV/RISCVPipeline.h b/backend/include/rcc/Target/RISCV/RISCVPipeline.h
index 50a6a68..3e8ea3d 100644
--- a/backend/include/rcc/Target/RISCV/RISCVPipeline.h
+++ b/backend/include/rcc/Target/RISCV/RISCVPipeline.h
@@ -17,6 +17,7 @@ namespace rcc {
 
 class MachineFunction;
 class TargetDescription;
+class TargetMachineOutlinerInfo;
 
 namespace riscv {
 
@@ -37,6 +38,8 @@ createCanonicalPipelinePass(std::string_view Name, const RISCVSubtarget &Subtarg
                             RISCVPipelineOptions Options = {});
 [[nodiscard]] Expected<std::vector<std::string>>
 canonicalPipelinePassNames(const MachineFunction &Function, const RISCVSubtarget &Subtarget);
+[[nodiscard]] Expected<std::unique_ptr<TargetMachineOutlinerInfo>>
+createMachineOutlinerInfo(bool FunctionSections, bool EnableRegisterSave);
 } // namespace riscv
 } // namespace rcc
 
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