From 77884c967d1cbc48afcbaef7e5a35adcb3c5da1b Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sat, 8 Aug 2026 04:14:34 +0800
Subject: [CodeGen] Implement machine SSA exit

---
 backend/include/rcc/Target/RISCV/RISCVCodeGen.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'backend/include/rcc/Target')

diff --git a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
index b06f20d..4db60f7 100644
--- a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
+++ b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
@@ -10,6 +10,7 @@ namespace rcc::riscv {
 [[nodiscard]] const TargetLegalizerInfo &legalizerInfo() noexcept;
 [[nodiscard]] const TargetRegisterBankInfo &registerBankInfo() noexcept;
 [[nodiscard]] const TargetInstructionSelector &instructionSelector() noexcept;
+[[nodiscard]] const TargetSSAInfo &ssaInfo() noexcept;
 
 } // namespace rcc::riscv
 
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