From f8daf08aba1f09c3024a70d3426891112d1662a2 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 12 Aug 2026 21:35:21 +0800
Subject: [RISCV] Consolidate instruction behavior in RISCVInstrInfo

---
 backend/include/rcc/Target/RISCV/RISCVCodeGen.h | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'backend/include/rcc/Target')

diff --git a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
index d68157a..6cda815 100644
--- a/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
+++ b/backend/include/rcc/Target/RISCV/RISCVCodeGen.h
@@ -7,7 +7,6 @@
 #include "rcc/CodeGen/MachineOptimizationPipeline.h"
 #include "rcc/CodeGen/TargetCodeGen.h"
 #include "rcc/CodeGen/TargetFrameLowering.h"
-#include "rcc/CodeGen/TargetInstrInfo.h"
 #include "rcc/CodeGen/TargetMemoryFolding.h"
 #include "rcc/CodeGen/TargetPseudoExpansion.h"
 #include "rcc/CodeGen/TargetRegisterAllocationInfo.h"
@@ -23,13 +22,11 @@ namespace rcc::riscv {
 createLegalizerInfo(RISCVSubtargetFeatures Features);
 [[nodiscard]] const TargetRegisterBankInfo &registerBankInfo() noexcept;
 [[nodiscard]] const TargetInstructionSelector &instructionSelector() noexcept;
-[[nodiscard]] const TargetSSAInfo &ssaInfo() noexcept;
 [[nodiscard]] const TargetRegisterAllocationInfo &registerAllocationInfo() noexcept;
 [[nodiscard]] const TargetFrameLowering &frameLowering() noexcept;
 [[nodiscard]] const TargetSchedulingModel &schedulingModel() noexcept;
 [[nodiscard]] const TargetMachineCombinerInfo &machineCombinerInfo() noexcept;
 [[nodiscard]] const TargetMemoryFoldingInfo &memoryFoldingInfo() noexcept;
-[[nodiscard]] const TargetInstrInfo &branchInfo() noexcept;
 [[nodiscard]] const TargetPseudoExpansionInfo &pseudoExpansionInfo() noexcept;
 [[nodiscard]] MachineOptimizationPipelineTargetInfo optimizationPipelineInfo() noexcept;
 
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