From c3932f55208e3fe2019d26a0e5af421c0b644872 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 25 Aug 2026 02:38:56 +0800 Subject: [RISCV] Implement make-compressible pass --- backend/include/rcc/CodeGen/MachineFunctionAttributes.h | 1 + backend/include/rcc/MIR/EmbeddedIR.h | 6 ++++++ 2 files changed, 7 insertions(+) (limited to 'backend/include/rcc') diff --git a/backend/include/rcc/CodeGen/MachineFunctionAttributes.h b/backend/include/rcc/CodeGen/MachineFunctionAttributes.h index 4344640..fd1d8d8 100644 --- a/backend/include/rcc/CodeGen/MachineFunctionAttributes.h +++ b/backend/include/rcc/CodeGen/MachineFunctionAttributes.h @@ -24,6 +24,7 @@ enum class MachineFunctionAttribute : std::uint8_t { IsOutlined, DebugInstrRef, TracksDebugUserValues, + MinSize, Count, }; diff --git a/backend/include/rcc/MIR/EmbeddedIR.h b/backend/include/rcc/MIR/EmbeddedIR.h index 80e512a..17b19cb 100644 --- a/backend/include/rcc/MIR/EmbeddedIR.h +++ b/backend/include/rcc/MIR/EmbeddedIR.h @@ -74,6 +74,10 @@ public: return HasSectionPrefix; } + [[nodiscard]] bool hasMinSize() const noexcept { + return HasMinSize; + } + [[nodiscard]] std::span blocks() const noexcept { return Blocks; } @@ -107,6 +111,8 @@ private: bool HasSection = false; bool HasComdat = false; bool HasSectionPrefix = false; + bool HasMinSize = false; + std::optional AttributeGroup; std::uint64_t NextUnnamedSlot = 0; std::vector Blocks; std::vector Allocas; -- cgit v1.2.3