From b85a348ab7bdd878fd975121fc2501625eceec95 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Fri, 14 Aug 2026 22:37:46 +0800 Subject: [GlobalISel] Legalize G_ABS --- .../rcc/CodeGen/GlobalISel/LegalizerHelper.h | 1 + .../include/rcc/CodeGen/GlobalISel/LegalizerInfo.h | 3 ++ backend/include/rcc/CodeGen/GlobalISel/Utils.h | 46 ++++++++++++---------- backend/include/rcc/CodeGen/MachineIRBuilder.h | 2 + backend/include/rcc/CodeGen/MachineOperand.h | 1 + 5 files changed, 32 insertions(+), 21 deletions(-) (limited to 'backend/include') diff --git a/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h b/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h index 19b3345..07ee8bb 100644 --- a/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h +++ b/backend/include/rcc/CodeGen/GlobalISel/LegalizerHelper.h @@ -28,6 +28,7 @@ public: const LegalizationDecision &Decision); [[nodiscard]] Expected lower(MachineInstr &Instruction, const LegalizationDecision &Decision); + [[nodiscard]] Expected lowerAbsToAddXor(MachineInstr &Instruction); [[nodiscard]] Expected lowerVAArg(MachineInstr &Instruction); [[nodiscard]] Expected widenScalar(MachineInstr &Instruction, std::size_t TypeIndex, LowLevelType WideType); diff --git a/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h b/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h index 9162526..2981f8e 100644 --- a/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h +++ b/backend/include/rcc/CodeGen/GlobalISel/LegalizerInfo.h @@ -24,6 +24,7 @@ class MachineFunction; class MachineInstr; class TargetDescription; class LegalizerHelper; +enum class GenericOpcode : std::uint32_t; enum class LegalizationAction : std::uint8_t { Legal, @@ -181,6 +182,8 @@ public: return true; } + [[nodiscard]] virtual GenericOpcode getExtOpcodeForWideningConstant(LowLevelType SmallType) const; + // This hook performs read-only target checks before a lowering mutation is committed. [[nodiscard]] virtual Expected validateLowering(const MachineInstr &, const MachineFunction &, diff --git a/backend/include/rcc/CodeGen/GlobalISel/Utils.h b/backend/include/rcc/CodeGen/GlobalISel/Utils.h index 5af2fb4..f252454 100644 --- a/backend/include/rcc/CodeGen/GlobalISel/Utils.h +++ b/backend/include/rcc/CodeGen/GlobalISel/Utils.h @@ -3,11 +3,13 @@ #ifndef RCC_CODEGEN_GLOBALISEL_UTILS_H #define RCC_CODEGEN_GLOBALISEL_UTILS_H +#include "rcc/ADT/APInt.h" #include "rcc/CodeGen/LowLevelType.h" #include "rcc/CodeGen/Register.h" #include "rcc/Support/Error.h" #include +#include #include #include @@ -18,36 +20,38 @@ class MachineInstr; class MachineRegisterInfo; class TargetDescription; +struct ValueAndVReg final { + APInt Value; + Register VReg; +}; + +[[nodiscard]] std::optional +getIConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI, + bool LookThroughInstrs = true); + /// Check whether an instruction only defines dead virtual registers and has no /// observable side effects. -[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction, - const MachineRegisterInfo &MRI, +[[nodiscard]] bool isTriviallyDead(const MachineInstr &Instruction, const MachineRegisterInfo &MRI, const TargetDescription &Target) noexcept; [[nodiscard]] Expected eraseInstrs(std::span Instructions, - MachineRegisterInfo &MRI, - const TargetDescription &Target); + MachineRegisterInfo &MRI, const TargetDescription &Target); -[[nodiscard]] Expected eraseInstr(MachineInstr &Instruction, - MachineRegisterInfo &MRI, +[[nodiscard]] Expected eraseInstr(MachineInstr &Instruction, MachineRegisterInfo &MRI, const TargetDescription &Target); -[[nodiscard]] Expected extractParts(Register Reg, LowLevelType Type, - int PartCount, +[[nodiscard]] Expected extractParts(Register Reg, LowLevelType Type, int PartCount, std::vector &Parts, - MachineIRBuilder &MIRBuilder, - MachineRegisterInfo &MRI); - -[[nodiscard]] Expected -extractParts(Register Reg, LowLevelType RegisterType, LowLevelType MainType, - LowLevelType &LeftoverType, std::vector &Parts, - std::vector &LeftoverParts, - MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); - -[[nodiscard]] Expected getLCMType(LowLevelType OriginalType, - LowLevelType TargetType); -[[nodiscard]] Expected getGCDType(LowLevelType OriginalType, - LowLevelType TargetType); + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +[[nodiscard]] Expected extractParts(Register Reg, LowLevelType RegisterType, + LowLevelType MainType, LowLevelType &LeftoverType, + std::vector &Parts, + std::vector &LeftoverParts, + MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI); + +[[nodiscard]] Expected getLCMType(LowLevelType OriginalType, LowLevelType TargetType); +[[nodiscard]] Expected getGCDType(LowLevelType OriginalType, LowLevelType TargetType); } // namespace rcc diff --git a/backend/include/rcc/CodeGen/MachineIRBuilder.h b/backend/include/rcc/CodeGen/MachineIRBuilder.h index 70a313a..e830837 100644 --- a/backend/include/rcc/CodeGen/MachineIRBuilder.h +++ b/backend/include/rcc/CodeGen/MachineIRBuilder.h @@ -202,6 +202,8 @@ public: Register Right) const; [[nodiscard]] Expected buildOr(Register Destination, Register Left, Register Right) const; + [[nodiscard]] Expected buildXor(Register Destination, Register Left, + Register Right) const; [[nodiscard]] Expected buildAdd(Register Destination, Register Left, Register Right) const; [[nodiscard]] Expected buildSub(Register Destination, Register Left, diff --git a/backend/include/rcc/CodeGen/MachineOperand.h b/backend/include/rcc/CodeGen/MachineOperand.h index db04795..1f321b0 100644 --- a/backend/include/rcc/CodeGen/MachineOperand.h +++ b/backend/include/rcc/CodeGen/MachineOperand.h @@ -384,6 +384,7 @@ public: [[nodiscard]] Expected setRegister(Register Reg); [[nodiscard]] Expected changeToImmediate(std::int64_t Value); [[nodiscard]] Expected setImmediate(std::int64_t Value); + [[nodiscard]] Expected setIntegerImmediate(APInt Value); [[nodiscard]] Expected setRegisterFlags(RegisterOperandFlags Flags); [[nodiscard]] Expected setSubReg(SubRegIndex SubReg); [[nodiscard]] Expected setBasicBlock(MachineBasicBlock &Block); -- cgit v1.2.3