From cd30fb546e389d1fb78ce8e579b3dba3a8fdb52a Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Thu, 13 Aug 2026 21:11:10 +0800 Subject: [CodeGen] Match LLVM machine copy propagation --- backend/include/rcc/CodeGen/MachineCopyPropagation.h | 14 ++++---------- backend/include/rcc/CodeGen/MachineOperand.h | 2 ++ .../include/rcc/CodeGen/MachineOptimizationPipeline.h | 7 ++++++- backend/include/rcc/CodeGen/TargetInstrInfo.h | 16 ++++++++++++++++ backend/include/rcc/Target/RISCV/RISCVPipeline.h | 10 ++++++++-- 5 files changed, 36 insertions(+), 13 deletions(-) (limited to 'backend/include') diff --git a/backend/include/rcc/CodeGen/MachineCopyPropagation.h b/backend/include/rcc/CodeGen/MachineCopyPropagation.h index ab8b23f..59a3a77 100644 --- a/backend/include/rcc/CodeGen/MachineCopyPropagation.h +++ b/backend/include/rcc/CodeGen/MachineCopyPropagation.h @@ -6,26 +6,21 @@ #include "rcc/CodeGen/MachinePassManager.h" #include -#include namespace rcc { class TargetInstrInfo; -enum class MachineCopyPropagationStage : std::uint8_t { - PreRegisterAllocation, - PostRegisterAllocation, -}; - struct MachineCopyPropagationOptions final { std::size_t MaximumPropagatedCopies = 10'000; + bool UseTargetCopyInstructions = false; }; class MachineCopyPropagationPass final : public MachineFunctionPass { public: - MachineCopyPropagationPass(const TargetInstrInfo &Info, MachineCopyPropagationStage Stage, - MachineCopyPropagationOptions Options = {}) noexcept - : Info(&Info), Stage(Stage), Options(Options) {} + explicit MachineCopyPropagationPass(const TargetInstrInfo &Info, + MachineCopyPropagationOptions Options = {}) noexcept + : Info(&Info), Options(Options) {} [[nodiscard]] const MachinePassContract &contract() const noexcept override; [[nodiscard]] Expected run(MachineFunction &Function, @@ -38,7 +33,6 @@ private: MachineActionReplay &Actions) const; const TargetInstrInfo *Info; - MachineCopyPropagationStage Stage; MachineCopyPropagationOptions Options; }; diff --git a/backend/include/rcc/CodeGen/MachineOperand.h b/backend/include/rcc/CodeGen/MachineOperand.h index ef14638..db04795 100644 --- a/backend/include/rcc/CodeGen/MachineOperand.h +++ b/backend/include/rcc/CodeGen/MachineOperand.h @@ -382,6 +382,8 @@ public: [[nodiscard]] bool isImplicit() const noexcept; [[nodiscard]] Expected setRegister(Register Reg); + [[nodiscard]] Expected changeToImmediate(std::int64_t Value); + [[nodiscard]] Expected setImmediate(std::int64_t Value); [[nodiscard]] Expected setRegisterFlags(RegisterOperandFlags Flags); [[nodiscard]] Expected setSubReg(SubRegIndex SubReg); [[nodiscard]] Expected setBasicBlock(MachineBasicBlock &Block); diff --git a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h index 51b4ed2..911cb86 100644 --- a/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h +++ b/backend/include/rcc/CodeGen/MachineOptimizationPipeline.h @@ -23,6 +23,10 @@ struct MachineOptimizationPipelineTargetInfo final { const TargetSchedulingModel &SchedulingModel; }; +struct MachineOptimizationPipelineOptions final { + bool UseTargetCopyInstructions = false; +}; + [[nodiscard]] Expected registerMachineOptimizationAnalyses(MachineFunctionAnalysisManager &Analyses); @@ -35,7 +39,8 @@ addSelectedSSAOptimizationPipeline(MachineFunctionPassManager &Pipeline, [[nodiscard]] Expected addPostRegisterAllocationPipeline(MachineFunctionPassManager &Pipeline, - const MachineOptimizationPipelineTargetInfo &TargetInfo); + const MachineOptimizationPipelineTargetInfo &TargetInfo, + MachineOptimizationPipelineOptions Options = {}); } // namespace rcc diff --git a/backend/include/rcc/CodeGen/TargetInstrInfo.h b/backend/include/rcc/CodeGen/TargetInstrInfo.h index 34752c5..8457ede 100644 --- a/backend/include/rcc/CodeGen/TargetInstrInfo.h +++ b/backend/include/rcc/CodeGen/TargetInstrInfo.h @@ -16,8 +16,14 @@ namespace rcc { class MachineBasicBlock; class MachineFunction; class MachineInstr; +class MachineOperand; class TargetDescription; +struct MachineCopyOperands final { + MachineOperand *Destination = nullptr; + MachineOperand *Source = nullptr; +}; + struct MachineBranchAnalysis final { MachineInstr *Conditional = nullptr; MachineInstr *Unconditional = nullptr; @@ -57,6 +63,16 @@ public: const MachineFunction &Function, const TargetDescription &Target) const = 0; + [[nodiscard]] virtual std::optional + getCopyOperands(MachineInstr &) const noexcept { + return std::nullopt; + } + + [[nodiscard]] virtual Expected simplifyInstruction(MachineInstr &, MachineFunction &, + const TargetDescription &) const { + return false; + } + [[nodiscard]] virtual Expected tryConvertToThreeAddress(MachineInstr &, std::size_t, std::size_t, MachineFunction &, const TargetDescription &) const { diff --git a/backend/include/rcc/Target/RISCV/RISCVPipeline.h b/backend/include/rcc/Target/RISCV/RISCVPipeline.h index 8b27032..267c497 100644 --- a/backend/include/rcc/Target/RISCV/RISCVPipeline.h +++ b/backend/include/rcc/Target/RISCV/RISCVPipeline.h @@ -19,11 +19,17 @@ class TargetDescription; namespace riscv { +struct RISCVPipelineOptions final { + bool UseTargetCopyInstructions = false; +}; + [[nodiscard]] Expected addCanonicalPipeline(MachineFunctionPassManager &Pipeline, const MachineFunction &Function, - const RISCVSubtarget &Subtarget); + const RISCVSubtarget &Subtarget, + RISCVPipelineOptions Options = {}); [[nodiscard]] Expected> -createCanonicalPipelinePass(std::string_view Name, const RISCVSubtarget &Subtarget); +createCanonicalPipelinePass(std::string_view Name, const RISCVSubtarget &Subtarget, + RISCVPipelineOptions Options = {}); [[nodiscard]] Expected> canonicalPipelinePassNames(const MachineFunction &Function, const RISCVSubtarget &Subtarget); } // namespace riscv -- cgit v1.2.3