From 1ff4fb953820c823ae8d5035c75bf43bf85e9c3c Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sat, 15 Aug 2026 04:23:23 +0800
Subject: [RISCV][GlobalISel] Legalize scalar bit count operations

---
 backend/lib/CodeGen/MachineIRBuilder.cpp | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'backend/lib/CodeGen/MachineIRBuilder.cpp')

diff --git a/backend/lib/CodeGen/MachineIRBuilder.cpp b/backend/lib/CodeGen/MachineIRBuilder.cpp
index 36f697b..8536490 100644
--- a/backend/lib/CodeGen/MachineIRBuilder.cpp
+++ b/backend/lib/CodeGen/MachineIRBuilder.cpp
@@ -858,6 +858,11 @@ Expected<MachineInstr *> MachineIRBuilder::buildAnyExtOrTrunc(MachineIRBuilderRe
   return buildExtOrTrunc(opcode(GenericOpcode::G_ANYEXT), Destination, Source);
 }
 
+Expected<MachineInstr *> MachineIRBuilder::buildZExtOrTrunc(MachineIRBuilderResult Destination,
+                                                            Register Source) const {
+  return buildExtOrTrunc(opcode(GenericOpcode::G_ZEXT), Destination, Source);
+}
+
 Expected<MachineInstr *> MachineIRBuilder::buildSExtOrTrunc(MachineIRBuilderResult Destination,
                                                             Register Source) const {
   return buildExtOrTrunc(opcode(GenericOpcode::G_SEXT), Destination, Source);
-- 
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