From 36b0be1ec1558f88d4f031a1817c3a4c2cba07a6 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sat, 22 Aug 2026 18:59:22 +0800 Subject: [CodeGen] Match LLVM machine debug stripping --- backend/lib/CodeGen/MachineInstr.cpp | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'backend/lib/CodeGen/MachineInstr.cpp') diff --git a/backend/lib/CodeGen/MachineInstr.cpp b/backend/lib/CodeGen/MachineInstr.cpp index f4602e0..55b4ce9 100644 --- a/backend/lib/CodeGen/MachineInstr.cpp +++ b/backend/lib/CodeGen/MachineInstr.cpp @@ -2,6 +2,7 @@ #include "rcc/CodeGen/MachineInstr.h" +#include "rcc/CodeGen/GenericOpcodes.h" #include "rcc/CodeGen/MachineBasicBlock.h" #include "rcc/CodeGen/MachineFunction.h" #include "rcc/CodeGen/MachineMemOperand.h" @@ -18,6 +19,14 @@ namespace rcc { +bool MachineInstr::isDebugInstr() const noexcept { + return InstructionOpcode == rcc::opcode(GenericOpcode::DBG_VALUE) || + InstructionOpcode == rcc::opcode(GenericOpcode::DBG_VALUE_LIST) || + InstructionOpcode == rcc::opcode(GenericOpcode::DBG_LABEL) || + InstructionOpcode == rcc::opcode(GenericOpcode::DBG_INSTR_REF) || + InstructionOpcode == rcc::opcode(GenericOpcode::DBG_PHI); +} + MachineInstr::MachineInstr(MachineFunction &OwnerFunction, Opcode InstructionOpcode, MachineInstrStableID StableID) : OwnerFunction(&OwnerFunction), InstructionOpcode(InstructionOpcode), StableID(StableID) {} @@ -97,6 +106,13 @@ Expected MachineInstr::insertOperand(std::size_t Index, MachineOperand &&O return makeUnexpected(ErrorCode::InvalidArgument, "register operand references an unknown virtual register"); } + if (Operand.isUse() && isDebugInstr()) { + RegisterOperandFlags RegisterFlags = Operand.registerFlags(); + RegisterFlags.set(RegisterOperandFlag::Debug); + auto Updated = Operand.setRegisterFlags(RegisterFlags); + if (!Updated) + return std::unexpected(Updated.error()); + } Operands.insert(Operands.begin() + static_cast(Index), std::move(Operand)); adjustTiesForInsertion(Index); -- cgit v1.2.3