From 1ef9d699d3160a9f79e89f423352fbb8d43e70d7 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Thu, 13 Aug 2026 19:04:49 +0800 Subject: [RISCV] Match LLVM register bank mappings --- backend/lib/CodeGen/MachineRegisterInfo.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'backend/lib/CodeGen/MachineRegisterInfo.cpp') diff --git a/backend/lib/CodeGen/MachineRegisterInfo.cpp b/backend/lib/CodeGen/MachineRegisterInfo.cpp index 2fe74d0..ccd7d89 100644 --- a/backend/lib/CodeGen/MachineRegisterInfo.cpp +++ b/backend/lib/CodeGen/MachineRegisterInfo.cpp @@ -255,6 +255,10 @@ RegOperandRange MachineRegisterInfo::regOperands(Register Reg) noexcept { return RegOperandRange(headFor(Reg), false, false, false); } +RegOperandRange MachineRegisterInfo::regOperands(Register Reg) const noexcept { + return RegOperandRange(headFor(Reg), false, false, false); +} + RegOperandRange MachineRegisterInfo::regNoDebugOperands(Register Reg) noexcept { return RegOperandRange(headFor(Reg), false, false, true); } -- cgit v1.2.3