From 432efe39315ed5ad0162f9c08dbf10941bc21dc1 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Mon, 3 Aug 2026 19:24:30 +0800
Subject: [CodeGen] Add target MIR text schema

---
 backend/lib/CodeGen/MachineRegisterInfo.cpp | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'backend/lib/CodeGen/MachineRegisterInfo.cpp')

diff --git a/backend/lib/CodeGen/MachineRegisterInfo.cpp b/backend/lib/CodeGen/MachineRegisterInfo.cpp
index c31b38b..3784b22 100644
--- a/backend/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/backend/lib/CodeGen/MachineRegisterInfo.cpp
@@ -94,6 +94,7 @@ Expected<void> MachineRegisterInfo::eraseVirtualRegister(Register Reg) {
   Info->get().Bank.reset();
   Info->get().RegClass.reset();
   Info->get().AllocationHints.clear();
+  Info->get().TargetFlags = 0;
   return {};
 }
 
@@ -188,6 +189,18 @@ Expected<void> MachineRegisterInfo::addAllocationHint(Register Reg, PhysicalRegi
   return {};
 }
 
+Expected<void> MachineRegisterInfo::setTargetRegisterFlags(Register Reg, std::uint8_t Flags) {
+  auto Info = virtualRegisterInfo(Reg);
+  if (!Info)
+    return std::unexpected(Info.error());
+  Info->get().TargetFlags = Flags;
+  return {};
+}
+
+Expected<void> MachineRegisterInfo::clearTargetRegisterFlags(Register Reg) {
+  return setTargetRegisterFlags(Reg, 0);
+}
+
 void MachineRegisterInfo::clearAllVirtualRegisterTypes() noexcept {
   for (VirtualRegisterInfo &Info : VirtualRegisters) {
     if (!Info.IsTombstone)
-- 
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