From f5d9ddc085055d28d6f9fb3730c3566097f43fb2 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Tue, 25 Aug 2026 03:11:23 +0800
Subject: [CodeGen] Implement the greedy register allocator pipeline

---
 backend/lib/CodeGen/VirtRegMap.cpp | 41 +++++++++++++++++++++++++++-----------
 1 file changed, 29 insertions(+), 12 deletions(-)

(limited to 'backend/lib/CodeGen/VirtRegMap.cpp')

diff --git a/backend/lib/CodeGen/VirtRegMap.cpp b/backend/lib/CodeGen/VirtRegMap.cpp
index 4f3ae45..b764667 100644
--- a/backend/lib/CodeGen/VirtRegMap.cpp
+++ b/backend/lib/CodeGen/VirtRegMap.cpp
@@ -236,6 +236,18 @@ Expected<bool> rewriteVirtualRegisters(MachineFunction &Function, const TargetDe
     auto SetRegister = Plan.Operand->setRegister(Plan.NewRegister);
     if (!SetRegister)
       return std::unexpected(SetRegister.error());
+    if (const auto Physical = Plan.NewRegister.physicalRegister()) {
+      const PhysicalRegisterDesc *Description = Target.registers().physicalRegister(*Physical);
+      if (Description != nullptr && !Description->IsConstant && !Description->IsArtificial &&
+          !Description->IsReserved && !Target.registers().isReservedRegister(*Physical) &&
+          !Function.registerInfo().isReserved(*Physical)) {
+        RegisterOperandFlags Flags = Plan.Operand->registerFlags();
+        Flags.set(RegisterOperandFlag::Renamable);
+        auto Updated = Plan.Operand->setRegisterFlags(Flags);
+        if (!Updated)
+          return std::unexpected(Updated.error());
+      }
+    }
     if (Plan.Operand->subReg().value() != 0) {
       auto Cleared = Plan.Operand->setSubReg(SubRegIndex{});
       if (!Cleared)
@@ -269,24 +281,29 @@ Expected<bool> rewriteVirtualRegisters(MachineFunction &Function, const TargetDe
 
 const MachinePassContract &VirtualRegisterRewritePass::contract() const noexcept {
   static const MachinePassContract Contract{
-      .Name = "VirtualRegisterRewrite",
-      .Requires = {MachineFunctionProperty::Selected, MachineFunctionProperty::NoPHIs,
-                   MachineFunctionProperty::TiedOpsRewritten},
+      .Name = "virtregrewriter",
+      .Requires = {MachineFunctionProperty::NoPHIs},
       .Sets = {MachineFunctionProperty::NoVRegs},
-      .Clears = {},
-      .RequiredAnalyses = {},
+      .Clears = {MachineFunctionProperty::IsSSA},
+      .RequiredAnalyses = {MachineFunctionAnalysisManager::id<VirtRegMapAnalysis>()},
       .VerificationStage = PipelineStage::RegisterAllocated,
   };
   return Contract;
 }
 
-Expected<MachinePassResult> VirtualRegisterRewritePass::run(MachineFunction &Function,
-                                                            const TargetDescription &Target,
-                                                            MachineFunctionAnalysisManager &) {
-  if (Mapping == nullptr)
-    return makeUnexpected(ErrorCode::InvalidArgument,
-                          "VirtualRegisterRewrite requires a VirtRegMap");
-  auto Rewritten = rewriteVirtualRegisters(Function, Target, *Mapping);
+Expected<VirtRegMapAnalysis::Result> VirtRegMapAnalysis::run(MachineFunction &Function,
+                                                             const TargetDescription &,
+                                                             MachineFunctionAnalysisManager &) {
+  return VirtRegMap(Function);
+}
+
+Expected<MachinePassResult>
+VirtualRegisterRewritePass::run(MachineFunction &Function, const TargetDescription &Target,
+                                MachineFunctionAnalysisManager &Analyses) {
+  auto Mapping = Analyses.getResult<VirtRegMapAnalysis>(Function, Target);
+  if (!Mapping)
+    return std::unexpected(Mapping.error());
+  auto Rewritten = rewriteVirtualRegisters(Function, Target, **Mapping);
   if (!Rewritten)
     return std::unexpected(Rewritten.error());
   MachinePassResult Result;
-- 
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