From 71988f9818677df0d90b19d4bb770ac8a6116e62 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 25 Aug 2026 02:21:25 +0800 Subject: [CodeGen] Implement RISC-V machine outlining --- backend/lib/Target/RISCV/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'backend/lib/Target/RISCV/CMakeLists.txt') diff --git a/backend/lib/Target/RISCV/CMakeLists.txt b/backend/lib/Target/RISCV/CMakeLists.txt index 97e6764..92a77a5 100644 --- a/backend/lib/Target/RISCV/CMakeLists.txt +++ b/backend/lib/Target/RISCV/CMakeLists.txt @@ -125,6 +125,7 @@ add_library( RISCVMergeBaseOffset.cpp RISCVMoveMerger.cpp RISCVOptimizationPipeline.cpp + RISCVOutliner.cpp RISCVPipeline.cpp RISCVPseudoExpansion.cpp RISCVRegisterAllocation.cpp -- cgit v1.2.3