From 9f7cd14951ed9b7e04176f68f5c454aa7018b3e3 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Thu, 13 Aug 2026 13:21:44 +0800
Subject: [RISCV] Use the generated opcode conversion

---
 backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

(limited to 'backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp')

diff --git a/backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index da8d687..541af2b 100644
--- a/backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/backend/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -31,10 +31,6 @@
 namespace rcc::riscv {
 namespace {
 
-[[nodiscard]] Opcode targetOpcode(InstructionOpcode Value) noexcept {
-  return Opcode::fromValue(static_cast<std::uint32_t>(Value));
-}
-
 [[nodiscard]] std::optional<LLT> registerType(const MachineFunction &Function,
                                               const MachineOperand &Operand) {
   const Register *Reg = Operand.getIf<Register>();
@@ -943,7 +939,7 @@ lowerAtomicCompareExchangeWithSuccess(MachineInstr &Instruction, MachineFunction
       Amount = *MaskedAmount;
     }
     auto SetOpcode =
-        Extension.setOpcode(Plan->SourceWidth == 32 ? targetOpcode(InstructionOpcode::G_SLLW)
+        Extension.setOpcode(Plan->SourceWidth == 32 ? instructionOpcode(InstructionOpcode::G_SLLW)
                                                     : opcode(GenericOpcode::G_SHL));
     if (!SetOpcode)
       return std::unexpected(SetOpcode.error());
-- 
cgit v1.2.3