From 1ef9d699d3160a9f79e89f423352fbb8d43e70d7 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Thu, 13 Aug 2026 19:04:49 +0800
Subject: [RISCV] Match LLVM register bank mappings

---
 backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

(limited to 'backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h')

diff --git a/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
index 543bc4d..69eb539 100644
--- a/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
+++ b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h
@@ -9,13 +9,15 @@ namespace rcc::riscv {
 
 class RISCVRegisterBankInfo final : public RegisterBankInfo {
 public:
-  [[nodiscard]] Expected<RegisterBankID> selectBank(const MachineFunction &Function, Register Reg,
-                                                    const VirtualRegisterInfo &Info,
-                                                    const MachineInstr *Instruction,
-                                                    const TargetDescription &Target) const override;
-  [[nodiscard]] Expected<void> constrainInstruction(MachineInstr &Instruction,
-                                                    MachineFunction &Function,
-                                                    const TargetDescription &Target) const override;
+  [[nodiscard]] Expected<RegisterBankSelection>
+  selectBank(const MachineFunction &Function, Register Reg, const VirtualRegisterInfo &Info,
+             const MachineInstr *Instruction, const TargetDescription &Target) const override;
+  [[nodiscard]] Expected<RegisterBankInstructionMapping>
+  getInstructionMapping(const MachineInstr &Instruction, const MachineFunction &Function,
+                        const TargetDescription &Target) const override;
+  [[nodiscard]] Expected<void> constrainSelectedInstruction(MachineInstr &Instruction,
+                                                            MachineFunction &Function,
+                                                            const TargetDescription &Target) const;
   [[nodiscard]] Expected<void> constrainRegister(MachineFunction &Function, Register Reg,
                                                  const TargetDescription &Target) const;
   [[nodiscard]] Expected<void> validateInstruction(const MachineInstr &Instruction,
-- 
cgit v1.2.3