From 3341938bb644e6fc39afa6a8fcb1306604999e42 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 22:37:49 +0800 Subject: [RISCV] Split the GlobalISel target components --- .../lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h (limited to 'backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h') diff --git a/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h new file mode 100644 index 0000000..543bc4d --- /dev/null +++ b/backend/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.h @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#ifndef RCC_LIB_TARGET_RISCV_GISEL_RISCVREGISTERBANKINFO_H +#define RCC_LIB_TARGET_RISCV_GISEL_RISCVREGISTERBANKINFO_H + +#include "rcc/CodeGen/RegisterBankInfo.h" + +namespace rcc::riscv { + +class RISCVRegisterBankInfo final : public RegisterBankInfo { +public: + [[nodiscard]] Expected selectBank(const MachineFunction &Function, Register Reg, + const VirtualRegisterInfo &Info, + const MachineInstr *Instruction, + const TargetDescription &Target) const override; + [[nodiscard]] Expected constrainInstruction(MachineInstr &Instruction, + MachineFunction &Function, + const TargetDescription &Target) const override; + [[nodiscard]] Expected constrainRegister(MachineFunction &Function, Register Reg, + const TargetDescription &Target) const; + [[nodiscard]] Expected validateInstruction(const MachineInstr &Instruction, + const MachineFunction &Function, + const TargetDescription &Target) const override; +}; + +} // namespace rcc::riscv + +#endif // RCC_LIB_TARGET_RISCV_GISEL_RISCVREGISTERBANKINFO_H -- cgit v1.2.3