From 3341938bb644e6fc39afa6a8fcb1306604999e42 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 22:37:49 +0800 Subject: [RISCV] Split the GlobalISel target components --- backend/lib/Target/RISCV/RISCV.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 backend/lib/Target/RISCV/RISCV.h (limited to 'backend/lib/Target/RISCV/RISCV.h') diff --git a/backend/lib/Target/RISCV/RISCV.h b/backend/lib/Target/RISCV/RISCV.h new file mode 100644 index 0000000..1a81f59 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCV.h @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-3.0-or-later + +#ifndef RCC_LIB_TARGET_RISCV_RISCV_H +#define RCC_LIB_TARGET_RISCV_RISCV_H + +#include "rcc/CodeGen/MachineCombinerPattern.h" +#include "rcc/CodeGen/MachineOptimizationPipeline.h" +#include "rcc/CodeGen/TargetFrameLowering.h" +#include "rcc/CodeGen/TargetMemoryFolding.h" +#include "rcc/CodeGen/TargetPseudoExpansion.h" +#include "rcc/CodeGen/TargetRegisterAllocationInfo.h" +#include "rcc/CodeGen/TargetSchedulingModel.h" +#include "rcc/Target/RISCV/RISCVSubtarget.h" + +namespace rcc { + +class InstructionSelector; + +namespace riscv { + +class RISCVRegisterBankInfo; +class RISCVSubtarget; + +[[nodiscard]] InstructionSelector * +createRISCVInstructionSelector(const RISCVSubtarget &Subtarget, + const RISCVRegisterBankInfo &RegisterBanks); +[[nodiscard]] const TargetRegisterAllocationInfo ®isterAllocationInfo() noexcept; +[[nodiscard]] const TargetFrameLowering &frameLowering() noexcept; +[[nodiscard]] const TargetSchedulingModel &schedulingModel() noexcept; +[[nodiscard]] const TargetMachineCombinerInfo &machineCombinerInfo() noexcept; +[[nodiscard]] const TargetMemoryFoldingInfo &memoryFoldingInfo() noexcept; +[[nodiscard]] const TargetPseudoExpansionInfo &pseudoExpansionInfo() noexcept; +[[nodiscard]] MachineOptimizationPipelineTargetInfo optimizationPipelineInfo() noexcept; + +} // namespace riscv +} // namespace rcc + +#endif // RCC_LIB_TARGET_RISCV_RISCV_H -- cgit v1.2.3