From 38626ed37c9ea78c76c12dae4806b750881fd910 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 11 Aug 2026 20:26:56 +0800 Subject: [RISCV] Add LP64 calling-convention facts --- backend/lib/Target/RISCV/RISCV.rccdesc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'backend/lib/Target/RISCV/RISCV.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index ad79073..93c94b4 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -237,6 +237,9 @@ register_classes: allocation_order: [X5, X6, X7, X28, X29, X30, X31, X10, X11, X12, X13, X14, X15, X16, X17, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X1] register_masks: + - + name: CSR_ILP32_LP64 + preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] - name: CSR_ILP32D_LP64D preserved: [X1, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, F8, F9, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27] @@ -252,6 +255,22 @@ mir_operand_flags: bitmask: [] calling_conventions: + - + id: 2 + symbol: LP64 + name: lp64 + integer_register_class: GPR + floating_register_class: FPR64 + integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] + floating_argument_registers: [] + integer_return_registers: [X10, X11] + floating_return_registers: [] + preserved_mask: CSR_ILP32_LP64 + stack_alignment_bytes: 16 + stack_argument_alignment_bytes: 16 + shadow_space_bytes: 0 + supports_varargs: true + supports_tail_calls: true - id: 1 symbol: LP64D -- cgit v1.2.3