From ce691f04c3eb1a972419187884f926de9632b7cf Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 03:33:45 +0800 Subject: [RISCV] Describe vector tuple registers --- backend/lib/Target/RISCV/RISCV.rccdesc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backend/lib/Target/RISCV/RISCV.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index f41d11b..c4a87e9 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -246,7 +246,7 @@ register_banks: - { id: 1, symbol: GPR, name: GPRB, maximum_size_bits: 64 } - { id: 2, symbol: FPR, name: FPRB, maximum_size_bits: 64 } - { id: 3, symbol: CSR, name: CSRB, maximum_size_bits: 32 } - - { id: 4, symbol: VR, name: VRB, maximum_size_bits: 64 } + - { id: 4, symbol: VR, name: VRB, maximum_size_bits: 512 } register_classes: - -- cgit v1.2.3