From 4f7b41c3c711d6c6fa4e422f3eec8961c91eea7a Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sun, 16 Aug 2026 15:39:45 +0800 Subject: tablegen: Generate GlobalISel match tables --- backend/lib/Target/RISCV/RISCVCallingConv.rccdesc | 33 +++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 backend/lib/Target/RISCV/RISCVCallingConv.rccdesc (limited to 'backend/lib/Target/RISCV/RISCVCallingConv.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc b/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc new file mode 100644 index 0000000..b222023 --- /dev/null +++ b/backend/lib/Target/RISCV/RISCVCallingConv.rccdesc @@ -0,0 +1,33 @@ +calling_conventions: + - + id: 2 + symbol: LP64 + name: lp64 + integer_register_class: GPR + floating_register_class: FPR64 + integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] + floating_argument_registers: [] + integer_return_registers: [X10, X11] + floating_return_registers: [] + preserved_mask: CSR_ILP32_LP64 + stack_alignment_bytes: 16 + stack_argument_alignment_bytes: 16 + shadow_space_bytes: 0 + supports_varargs: true + supports_tail_calls: true + - + id: 1 + symbol: LP64D + name: lp64d + integer_register_class: GPR + floating_register_class: FPR64 + integer_argument_registers: [X10, X11, X12, X13, X14, X15, X16, X17] + floating_argument_registers: [F10_D, F11_D, F12_D, F13_D, F14_D, F15_D, F16_D, F17_D] + integer_return_registers: [X10, X11] + floating_return_registers: [F10_D, F11_D] + preserved_mask: CSR_ILP32D_LP64D + stack_alignment_bytes: 16 + stack_argument_alignment_bytes: 16 + shadow_space_bytes: 0 + supports_varargs: true + supports_tail_calls: true -- cgit v1.2.3