From 219b315373ef34ca20cc78b89bf3c3d19442ffbd Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 19 Aug 2026 03:41:05 +0800 Subject: [RISCV][GlobalISel] Generate integer load selection --- .../lib/Target/RISCV/RISCVGISelAddressing.rccdesc | 190 +++++++++++++++++++++ 1 file changed, 190 insertions(+) (limited to 'backend/lib/Target/RISCV/RISCVGISelAddressing.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCVGISelAddressing.rccdesc b/backend/lib/Target/RISCV/RISCVGISelAddressing.rccdesc index f69ab81..1ff9593 100644 --- a/backend/lib/Target/RISCV/RISCVGISelAddressing.rccdesc +++ b/backend/lib/Target/RISCV/RISCVGISelAddressing.rccdesc @@ -1,6 +1,196 @@ # SPDX-License-Identifier: GPL-3.0-or-later selection_rules: + - + id: select_g_load_m8 + priority: 300 + match: + opcode: G_LOAD + memory: { index: 0, bytes: 1 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LBU + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_load_m16 + priority: 300 + match: + opcode: G_LOAD + memory: { index: 0, bytes: 2 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LH + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_load_m32 + priority: 300 + match: + opcode: G_LOAD + memory: { index: 0, bytes: 4 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LW + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_load_m64 + priority: 300 + match: + opcode: G_LOAD + memory: { index: 0, bytes: 8 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LD + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_sextload_m8 + priority: 300 + match: + opcode: G_SEXTLOAD + memory: { index: 0, bytes: 1 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LB + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_sextload_m16 + priority: 300 + match: + opcode: G_SEXTLOAD + memory: { index: 0, bytes: 2 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LH + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_sextload_m32 + priority: 300 + match: + opcode: G_SEXTLOAD + memory: { index: 0, bytes: 4 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LW + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_zextload_m8 + priority: 300 + match: + opcode: G_ZEXTLOAD + memory: { index: 0, bytes: 1 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LBU + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_zextload_m16 + priority: 300 + match: + opcode: G_ZEXTLOAD + memory: { index: 0, bytes: 2 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LHU + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } + - + id: select_g_zextload_m32 + priority: 300 + match: + opcode: G_ZEXTLOAD + memory: { index: 0, bytes: 4 } + operand_types: + - { index: 1, kind: pointer, bits: 64 } + operand_banks: + - { index: 0, bank: GPR } + - { index: 1, bank: GPR } + apply: + instructions: + - opcode: LWU + root: true + operands: + - { operand: 0 } + - { complex: addr_reg_imm_base, operand: 1 } + - { complex: addr_reg_imm_offset, operand: 1 } - id: select_g_frame_index priority: 100 -- cgit v1.2.3