From 8a4bb6e3b0bffa0ed79b51347b12ee4293b622a7 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Sat, 22 Aug 2026 18:49:08 +0800 Subject: [CodeGen] Generate RISC-V macro fusion rules --- backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc index 7bb30e5..13ea700 100644 --- a/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc +++ b/backend/lib/Target/RISCV/RISCVInstrInfoI.rccdesc @@ -188,7 +188,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -233,7 +233,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -248,7 +248,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -263,7 +263,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 @@ -666,7 +666,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS2 } num_explicit_defs: 1 - flags: [produces_code] + flags: [produces_code, commutable] scheduling_class: ALU encoding_category: R assembly_format: RD_RS1_RS2 -- cgit v1.2.3