From 36c4344ddf1866005c62910166ca077bf2e8f62e Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 26 Aug 2026 17:38:21 +0800 Subject: [CodeGen] Implement RISC-V finalize-isel --- backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc index 41cc051..a0767f9 100644 --- a/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVInstrInfoPseudo.rccdesc @@ -186,7 +186,7 @@ instructions: - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } - { kinds: [register], role: use, register_class: GPR, register_bank: GPR } num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer] + flags: [pseudo, produces_code, allowed_pre_legalizer, uses_custom_inserter] owner: instruction_select deadline: selected - @@ -201,7 +201,7 @@ instructions: - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR } - { kinds: [register], role: use, register_class: FPR32, register_bank: FPR } num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer] + flags: [pseudo, produces_code, allowed_pre_legalizer, uses_custom_inserter] owner: instruction_select deadline: selected - @@ -216,7 +216,7 @@ instructions: - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR } - { kinds: [register], role: use, register_class: FPR64, register_bank: FPR } num_explicit_defs: 1 - flags: [pseudo, produces_code, allowed_pre_legalizer] + flags: [pseudo, produces_code, allowed_pre_legalizer, uses_custom_inserter] owner: instruction_select deadline: selected - -- cgit v1.2.3