From 75f1223070749b0df3002226ebbb474c68c71f90 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sat, 22 Aug 2026 19:16:18 +0800
Subject: [RISCV] Generate MC pseudo lowering

---
 .../lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc

(limited to 'backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc')

diff --git a/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc b/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc
new file mode 100644
index 0000000..a505281
--- /dev/null
+++ b/backend/lib/Target/RISCV/RISCVMCPseudoLowering.rccdesc
@@ -0,0 +1,35 @@
+mc_pseudo_expansions:
+  -
+    pseudo: PseudoBR
+    opcode: JAL
+    operands:
+      - { register: X0 }
+      - { operand: 0 }
+  -
+    pseudo: PseudoBRIND
+    opcode: JALR
+    operands:
+      - { register: X0 }
+      - { operand: 0 }
+      - { operand: 1 }
+  -
+    pseudo: PseudoRET
+    opcode: JALR
+    operands:
+      - { register: X0 }
+      - { register: X1 }
+      - { immediate: 0 }
+  -
+    pseudo: ReadFFLAGS
+    opcode: CSRRS
+    operands:
+      - { operand: 0 }
+      - { immediate: 1 }
+      - { register: X0 }
+  -
+    pseudo: WriteFFLAGS
+    opcode: CSRRW
+    operands:
+      - { register: X0 }
+      - { immediate: 1 }
+      - { operand: 0 }
-- 
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