From 495c675771f43cfa12ab7a426a538be72fec1805 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 17:03:19 +0800
Subject: [CodeGen] Implement machine optimization and scheduling

---
 backend/lib/Target/RISCV/RISCVMachineCombiner.cpp | 92 +++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 backend/lib/Target/RISCV/RISCVMachineCombiner.cpp

(limited to 'backend/lib/Target/RISCV/RISCVMachineCombiner.cpp')

diff --git a/backend/lib/Target/RISCV/RISCVMachineCombiner.cpp b/backend/lib/Target/RISCV/RISCVMachineCombiner.cpp
new file mode 100644
index 0000000..5c22dde
--- /dev/null
+++ b/backend/lib/Target/RISCV/RISCVMachineCombiner.cpp
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+#include "rcc/Target/RISCV/RISCVCodeGen.h"
+#include "rcc/Target/RISCV/RISCVTarget.h"
+
+#include <cstdint>
+#include <cstdlib>
+#include <string>
+#include <utility>
+#include <vector>
+
+namespace rcc::riscv {
+namespace {
+
+[[nodiscard]] constexpr Opcode targetOpcode(InstructionOpcode Value) noexcept {
+  return Opcode::fromValue(static_cast<std::uint32_t>(Value));
+}
+
+[[nodiscard]] constexpr MachineCombinerStageMask allOptimizationStages() noexcept {
+  return machineCombinerStageMask(MachineCombinerStage::SelectedSSA) |
+         machineCombinerStageMask(MachineCombinerStage::PreRegisterAllocation) |
+         machineCombinerStageMask(MachineCombinerStage::PostRegisterAllocation) |
+         machineCombinerStageMask(MachineCombinerStage::PostFrame);
+}
+
+[[nodiscard]] MachineCombinerPattern immediateIdentity(InstructionOpcode OpcodeValue,
+                                                       std::string Name, std::int64_t Immediate) {
+  return {
+      .Name = std::move(Name),
+      .RootOpcode = targetOpcode(OpcodeValue),
+      .Stages = allOptimizationStages(),
+      .Predicates = {{MachineCombinerPredicateKind::ImmediateEquals, 2, 0, Immediate}},
+      .Action = {MachineCombinerActionKind::ReplaceDefWithOperandAndErase, 0, 1},
+  };
+}
+
+[[nodiscard]] MachineCombinerPattern zeroRegisterIdentity(InstructionOpcode OpcodeValue,
+                                                          std::string Name, std::size_t ZeroOperand,
+                                                          std::size_t SourceOperand) {
+  return {
+      .Name = std::move(Name),
+      .RootOpcode = targetOpcode(OpcodeValue),
+      .Stages = allOptimizationStages(),
+      .Predicates = {{MachineCombinerPredicateKind::PhysicalRegisterEquals, ZeroOperand, 0,
+                      static_cast<std::int64_t>(PhysicalRegisterID::X0)}},
+      .Action = {MachineCombinerActionKind::ReplaceDefWithOperandAndErase, 0, SourceOperand},
+  };
+}
+
+[[nodiscard]] MachineCombinerPattern equalSourceIdentity(InstructionOpcode OpcodeValue,
+                                                         std::string Name) {
+  return {
+      .Name = std::move(Name),
+      .RootOpcode = targetOpcode(OpcodeValue),
+      .Stages = allOptimizationStages(),
+      .Predicates = {{MachineCombinerPredicateKind::RegisterEquals, 1, 2, 0}},
+      .Action = {MachineCombinerActionKind::ReplaceDefWithOperandAndErase, 0, 1},
+  };
+}
+
+[[nodiscard]] std::vector<MachineCombinerPattern> createPatterns() {
+  std::vector<MachineCombinerPattern> Patterns;
+  Patterns.push_back(immediateIdentity(InstructionOpcode::ADDI, "addi-zero", 0));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::XORI, "xori-zero", 0));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::ORI, "ori-zero", 0));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::ANDI, "andi-all-ones", -1));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::SLLI, "slli-zero", 0));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::SRLI, "srli-zero", 0));
+  Patterns.push_back(immediateIdentity(InstructionOpcode::SRAI, "srai-zero", 0));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::ADD, "add-zero-right", 2, 1));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::ADD, "add-zero-left", 1, 2));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::OR, "or-zero-right", 2, 1));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::OR, "or-zero-left", 1, 2));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::XOR, "xor-zero-right", 2, 1));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::XOR, "xor-zero-left", 1, 2));
+  Patterns.push_back(zeroRegisterIdentity(InstructionOpcode::SUB, "sub-zero-right", 2, 1));
+  Patterns.push_back(equalSourceIdentity(InstructionOpcode::FSGNJ_S, "fsgnj-s-copy"));
+  Patterns.push_back(equalSourceIdentity(InstructionOpcode::FSGNJ_D, "fsgnj-d-copy"));
+  return Patterns;
+}
+
+} // namespace
+
+const TargetMachineCombinerInfo &machineCombinerInfo() noexcept {
+  static const Expected<TargetMachineCombinerInfo> Info =
+      TargetMachineCombinerInfo::create(createPatterns());
+  if (!Info)
+    std::abort();
+  return *Info;
+}
+
+} // namespace rcc::riscv
-- 
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