From 81afb6570000472c182e5b1f540f69382602aaad Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Mon, 24 Aug 2026 17:30:29 +0800
Subject: [RISCV] Match LLVM emergency spill layout

---
 backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp')

diff --git a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
index cfc5583..45c557a 100644
--- a/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVOptimizationPipeline.cpp
@@ -5,8 +5,9 @@
 
 namespace rcc::riscv {
 
-MachineOptimizationPipelineTargetInfo
-optimizationPipelineInfo(const RISCVSubtarget &Subtarget, bool EmitSchedulerDebugOutput) noexcept {
+MachineOptimizationPipelineTargetInfo optimizationPipelineInfo(const RISCVSubtarget &Subtarget,
+                                                               bool EmitSchedulerDebugOutput,
+                                                               bool EmitFrameDebugOutput) noexcept {
   return {
       .InstrInfo = instrInfo(),
       .Combiner = machineCombinerInfo(),
@@ -15,6 +16,7 @@ optimizationPipelineInfo(const RISCVSubtarget &Subtarget, bool EmitSchedulerDebu
       .PseudoExpansion = pseudoExpansionInfo(),
       .SchedulingModel = Subtarget.schedulingModel(),
       .SchedulerOptions = {.EmitDebugOutput = EmitSchedulerDebugOutput},
+      .FrameOptions = {.EmitDebugOutput = EmitFrameDebugOutput},
   };
 }
 
-- 
cgit v1.2.3