From f5d9ddc085055d28d6f9fb3730c3566097f43fb2 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 25 Aug 2026 03:11:23 +0800 Subject: [CodeGen] Implement the greedy register allocator pipeline --- backend/lib/Target/RISCV/RISCVPipeline.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'backend/lib/Target/RISCV/RISCVPipeline.cpp') diff --git a/backend/lib/Target/RISCV/RISCVPipeline.cpp b/backend/lib/Target/RISCV/RISCVPipeline.cpp index 854417a..1e18661 100644 --- a/backend/lib/Target/RISCV/RISCVPipeline.cpp +++ b/backend/lib/Target/RISCV/RISCVPipeline.cpp @@ -15,9 +15,11 @@ #include "rcc/CodeGen/MachineOptimizationPipeline.h" #include "rcc/CodeGen/MachinePseudoExpansion.h" #include "rcc/CodeGen/PHIElimination.h" +#include "rcc/CodeGen/RegAllocCommon.h" #include "rcc/CodeGen/RegAllocPBQP.h" #include "rcc/CodeGen/TargetDescription.h" #include "rcc/CodeGen/TwoAddressInstructionPass.h" +#include "rcc/CodeGen/VirtRegMap.h" #include #include @@ -86,7 +88,10 @@ template Options.DebugPrologueEpilogue)); if (!Added) return std::unexpected(Added.error()); - return addPass(Pipeline, registerAllocationInfo()); + Added = addPass(Pipeline, registerAllocationInfo()); + if (!Added) + return std::unexpected(Added.error()); + return addPass(Pipeline); } [[nodiscard]] Expected addCompleteRegistry(MachineFunctionPassManager &Pipeline, @@ -96,6 +101,9 @@ template if (!Added) return std::unexpected(Added.error()); Added = addSSAExitPipeline(Pipeline, Subtarget, Options); + if (!Added) + return std::unexpected(Added.error()); + Added = Pipeline.addPass(createGreedyAllocatorPass(registerAllocationInfo())); if (!Added) return std::unexpected(Added.error()); Added = addRegisterAllocationPipeline(Pipeline, Subtarget, Options); -- cgit v1.2.3