From 551f0b3fcd6f797ed6dca90f39123b0359396dcb Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Tue, 11 Aug 2026 20:08:36 +0800
Subject: [RISCV] Match LLVM call-frame pseudo semantics

---
 .../lib/Target/RISCV/RISCVRegisterAllocation.cpp   | 32 ----------------------
 1 file changed, 32 deletions(-)

(limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp')

diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index 81fc6dc..aee09a9 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -14,7 +14,6 @@
 
 #include <algorithm>
 #include <array>
-#include <bit>
 #include <cstddef>
 #include <cstdint>
 #include <optional>
@@ -37,20 +36,6 @@ struct SpillForm final {
   return RegisterClassID::fromValue(static_cast<std::uint32_t>(Value));
 }
 
-[[nodiscard]] std::optional<std::int64_t> immediateValue(const MachineOperand &Operand) noexcept {
-  if (const auto *Immediate = Operand.getIf<std::int64_t>())
-    return *Immediate;
-  const auto *Integer = Operand.getIf<IntegerImmediateOperand>();
-  if (Integer == nullptr || Integer->Value.bitWidth() == 0 || Integer->Value.bitWidth() > 64) {
-    return std::nullopt;
-  }
-  std::uint64_t Raw = Integer->Value.words().empty() ? 0 : Integer->Value.words().front();
-  const std::uint32_t Width = Integer->Value.bitWidth();
-  if (Width < 64 && (Raw & (std::uint64_t{1} << (Width - 1U))) != 0)
-    Raw |= ~std::uint64_t{0} << Width;
-  return std::bit_cast<std::int64_t>(Raw);
-}
-
 [[nodiscard]] constexpr std::optional<SpillForm> spillForm(RegisterClassID Class) noexcept {
   if (Class == registerClassID(RegisterClass::GPR) ||
       Class == registerClassID(RegisterClass::GPRC) ||
@@ -129,23 +114,6 @@ public:
         RequiredAlignment = std::max(RequiredAlignment, Object.description()->Align.bytes());
       }
     }
-    for (const MachineBasicBlock *Block = Function.firstBlock(); Block != nullptr;
-         Block = Block->next()) {
-      for (const MachineInstr *Instruction = Block->firstInstruction(); Instruction != nullptr;
-           Instruction = Instruction->next()) {
-        if (Instruction->opcode() != targetOpcode(InstructionOpcode::ADJCALLSTACKDOWN) &&
-            Instruction->opcode() != targetOpcode(InstructionOpcode::ADJCALLSTACKUP)) {
-          continue;
-        }
-        if (Instruction->operandCount() < 2)
-          continue;
-        const auto Requested = immediateValue(*Instruction->operandAt(1));
-        if (Requested && *Requested > 0 &&
-            std::has_single_bit(static_cast<std::uint64_t>(*Requested))) {
-          RequiredAlignment = std::max(RequiredAlignment, static_cast<std::uint64_t>(*Requested));
-        }
-      }
-    }
     const bool RequiresRealignment = RequiredAlignment > 16;
     if (Reg.number() == static_cast<std::uint32_t>(PhysicalRegisterID::X9))
       return RequiresRealignment;
-- 
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