From 705ebca5d37ee30e9cd517fed5f09dbf12113e6b Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 02:35:25 +0800 Subject: [RISCV] Make target memory operands optional --- backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp') diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp index 055b67b..d14e802 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp +++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp @@ -178,9 +178,11 @@ public: for (const InstructionOpcode OpcodeValue : {Form->Load, Form->Store}) { const InstructionDescriptor *Instruction = Target.instructionDescriptor(targetOpcode(OpcodeValue)); + const InstructionFlag MemoryFlag = + OpcodeValue == Form->Load ? InstructionFlag::MayLoad : InstructionFlag::MayStore; if (Instruction == nullptr || Instruction->Operands.size() != 3 || !Instruction->Operands[1].Kinds.contains(MachineOperand::Kind::FrameIndex) || - !Instruction->RequiresMemoryOperands) { + !Instruction->Flags.has(MemoryFlag)) { return makeUnexpected(ErrorCode::InternalError, "RV64GC spill instruction descriptor is incomplete"); } -- cgit v1.2.3