From f5d9ddc085055d28d6f9fb3730c3566097f43fb2 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 25 Aug 2026 03:11:23 +0800 Subject: [CodeGen] Implement the greedy register allocator pipeline --- backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp') diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp index 99c261c..2b34f53 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp +++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp @@ -60,10 +60,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory auto Align = Alignment::create(AlignmentInBytes); if (!Align) return std::unexpected(Align.error()); + auto Type = LowLevelType::makeCategoryNeutralScalar(SizeInBytes * 8U); + if (!Type) + return std::unexpected(Type.error()); MachineMemOperandDesc Description; Description.Accesses = {Access}; Description.Size = *Size; + Description.MemoryType = *Type; Description.Align = *Align; Description.Base = MemoryBase::frameIndex(StackSlot); return Builder.function().createMemOperand(std::move(Description)); -- cgit v1.2.3