From 9e89d1d718977749ca798b27b7ad45e1781602c2 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 25 Aug 2026 01:43:04 +0800 Subject: [RISCV] Implement Zcmp move merging --- backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc') diff --git a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc index 9e5a237..4806ec4 100644 --- a/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc +++ b/backend/lib/Target/RISCV/RISCVRegisterInfo.rccdesc @@ -378,6 +378,18 @@ register_classes: lanes: 1 registers: [X6, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31] allocation_order: [X10, X11, X12, X13, X14, X15, X16, X17, X6, X28, X29, X30, X31, X8, X9, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27] + - + id: 13 + symbol: SR07 + name: SR07 + bank: GPR + superclasses: [GPR] + size_bits: 64 + spill_size_bits: 64 + spill_alignment_bits: 64 + lanes: 1 + registers: [X8, X9, X18, X19, X20, X21, X22, X23] + allocation_order: [X8, X9, X18, X19, X20, X21, X22, X23] register_masks: - -- cgit v1.2.3