From 6c97d54954112be9a5badacaec8efa1d05bd7d15 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Wed, 19 Aug 2026 02:50:30 +0800
Subject: [RISCV][GlobalISel] Generate indirect branch selection

---
 backend/lib/Target/RISCV/RISCVTarget.cpp | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

(limited to 'backend/lib/Target/RISCV/RISCVTarget.cpp')

diff --git a/backend/lib/Target/RISCV/RISCVTarget.cpp b/backend/lib/Target/RISCV/RISCVTarget.cpp
index 0c202a2..4f33ce3 100644
--- a/backend/lib/Target/RISCV/RISCVTarget.cpp
+++ b/backend/lib/Target/RISCV/RISCVTarget.cpp
@@ -43,11 +43,21 @@ physicalRegisters(std::initializer_list<PhysicalRegisterID> IDs) {
   return Result;
 }
 
+[[nodiscard]] std::vector<RegisterClassID>
+registerClasses(std::initializer_list<RegisterClass> IDs) {
+  std::vector<RegisterClassID> Result;
+  Result.reserve(IDs.size());
+  for (const RegisterClass ID : IDs)
+    Result.push_back(RegisterClassID::fromValue(static_cast<std::uint32_t>(ID)));
+  return Result;
+}
+
 [[nodiscard]] RegisterClassDesc registerClass(
     RegisterClass ID, const char *Name, std::initializer_list<PhysicalRegisterID> Registers,
-    std::initializer_list<PhysicalRegisterID> AllocationOrder, RegisterBank Bank,
-    std::uint32_t SizeInBits, std::uint32_t SpillSizeInBits, std::uint32_t SpillAlignmentInBits,
-    std::uint64_t Lanes, bool Allocatable, std::uint32_t CopyCost) {
+    std::initializer_list<PhysicalRegisterID> AllocationOrder,
+    std::initializer_list<RegisterClass> SuperClasses, RegisterBank Bank, std::uint32_t SizeInBits,
+    std::uint32_t SpillSizeInBits, std::uint32_t SpillAlignmentInBits, std::uint64_t Lanes,
+    bool Allocatable, std::uint32_t CopyCost) {
   return {
       .ID = RegisterClassID::fromValue(static_cast<std::uint32_t>(ID)),
       .Name = Name,
@@ -58,7 +68,7 @@ physicalRegisters(std::initializer_list<PhysicalRegisterID> IDs) {
       .SpillAlignmentInBits = SpillAlignmentInBits,
       .Lanes = LaneMask::fromRaw(Lanes),
       .SupportedSubRegs = {},
-      .SuperClasses = {},
+      .SuperClasses = registerClasses(SuperClasses),
       .DefaultBank = RegisterBankID::fromValue(static_cast<std::uint32_t>(Bank)),
       .Allocatable = Allocatable,
       .CopyCost = CopyCost,
-- 
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