From 4937c5107848f1c60262ef729d466e8d90df8d47 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 01:36:47 +0800 Subject: [RISCV] Allow frame indices in ADDI --- backend/lib/Target/RISCV/RISCV.rccdesc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'backend/lib/Target/RISCV') diff --git a/backend/lib/Target/RISCV/RISCV.rccdesc b/backend/lib/Target/RISCV/RISCV.rccdesc index bf5c288..8325777 100644 --- a/backend/lib/Target/RISCV/RISCV.rccdesc +++ b/backend/lib/Target/RISCV/RISCV.rccdesc @@ -488,7 +488,7 @@ instructions: encoding: 1344531 operands: - { kinds: [register], role: def, register_class: GPR, register_bank: GPR, name: RD } - - { kinds: [register], role: use, register_class: GPR, register_bank: GPR, name: RS1 } + - { kinds: [register, frame_index], role: use, register_class: GPR, register_bank: GPR, name: RS1 } - { kinds: [immediate, constant_pool_index, jump_table_index, global_symbol, external_symbol, block_address, mc_symbol], immediate_predicate: SIMM12, allowed_target_flags: 68, name: IMM } num_explicit_defs: 1 flags: [produces_code, rematerializable] -- cgit v1.2.3