From f5d9ddc085055d28d6f9fb3730c3566097f43fb2 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Tue, 25 Aug 2026 03:11:23 +0800
Subject: [CodeGen] Implement the greedy register allocator pipeline

---
 backend/lib/Target/RISCV/RISCVPipeline.cpp           | 10 +++++++++-
 backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp |  4 ++++
 2 files changed, 13 insertions(+), 1 deletion(-)

(limited to 'backend/lib/Target')

diff --git a/backend/lib/Target/RISCV/RISCVPipeline.cpp b/backend/lib/Target/RISCV/RISCVPipeline.cpp
index 854417a..1e18661 100644
--- a/backend/lib/Target/RISCV/RISCVPipeline.cpp
+++ b/backend/lib/Target/RISCV/RISCVPipeline.cpp
@@ -15,9 +15,11 @@
 #include "rcc/CodeGen/MachineOptimizationPipeline.h"
 #include "rcc/CodeGen/MachinePseudoExpansion.h"
 #include "rcc/CodeGen/PHIElimination.h"
+#include "rcc/CodeGen/RegAllocCommon.h"
 #include "rcc/CodeGen/RegAllocPBQP.h"
 #include "rcc/CodeGen/TargetDescription.h"
 #include "rcc/CodeGen/TwoAddressInstructionPass.h"
+#include "rcc/CodeGen/VirtRegMap.h"
 
 #include <memory>
 #include <ranges>
@@ -86,7 +88,10 @@ template <typename PassT, typename... ArgumentT>
                                          Options.DebugPrologueEpilogue));
   if (!Added)
     return std::unexpected(Added.error());
-  return addPass<PBQPAllocatorPass>(Pipeline, registerAllocationInfo());
+  Added = addPass<PBQPAllocatorPass>(Pipeline, registerAllocationInfo());
+  if (!Added)
+    return std::unexpected(Added.error());
+  return addPass<VirtualRegisterRewritePass>(Pipeline);
 }
 
 [[nodiscard]] Expected<void> addCompleteRegistry(MachineFunctionPassManager &Pipeline,
@@ -96,6 +101,9 @@ template <typename PassT, typename... ArgumentT>
   if (!Added)
     return std::unexpected(Added.error());
   Added = addSSAExitPipeline(Pipeline, Subtarget, Options);
+  if (!Added)
+    return std::unexpected(Added.error());
+  Added = Pipeline.addPass(createGreedyAllocatorPass(registerAllocationInfo()));
   if (!Added)
     return std::unexpected(Added.error());
   Added = addRegisterAllocationPipeline(Pipeline, Subtarget, Options);
diff --git a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
index 99c261c..2b34f53 100644
--- a/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
+++ b/backend/lib/Target/RISCV/RISCVRegisterAllocation.cpp
@@ -60,10 +60,14 @@ createStackMemoryOperand(MachineIRBuilder &Builder, FrameIndex StackSlot, Memory
   auto Align = Alignment::create(AlignmentInBytes);
   if (!Align)
     return std::unexpected(Align.error());
+  auto Type = LowLevelType::makeCategoryNeutralScalar(SizeInBytes * 8U);
+  if (!Type)
+    return std::unexpected(Type.error());
 
   MachineMemOperandDesc Description;
   Description.Accesses = {Access};
   Description.Size = *Size;
+  Description.MemoryType = *Type;
   Description.Align = *Align;
   Description.Base = MemoryBase::frameIndex(StackSlot);
   return Builder.function().createMemOperand(std::move(Description));
-- 
cgit v1.2.3