From 81afb6570000472c182e5b1f540f69382602aaad Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Mon, 24 Aug 2026 17:30:29 +0800 Subject: [RISCV] Match LLVM emergency spill layout --- backend/lib/Tooling/PipelineDriver.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'backend/lib/Tooling') diff --git a/backend/lib/Tooling/PipelineDriver.cpp b/backend/lib/Tooling/PipelineDriver.cpp index 5bf57cf..ebba1b6 100644 --- a/backend/lib/Tooling/PipelineDriver.cpp +++ b/backend/lib/Tooling/PipelineDriver.cpp @@ -128,13 +128,15 @@ createPasses(const MachineFunction &Function, const BackendInvocation &Invocatio } MachineFunctionPassManager Pipeline(Options); const bool DebugMachineScheduler = hasDebugType(Invocation, "machine-scheduler"); + const bool DebugPrologueEpilogue = hasDebugType(Invocation, "prologepilog"); if (Invocation.PassPipeline.size() == 1 && Invocation.PassPipeline.front() == "default") { auto Added = riscv::addCanonicalPipeline( Pipeline, Function, Subtarget, riscv::RISCVPipelineOptions{.Optimization = Invocation.Optimization, .UseTargetCopyInstructions = true, .GlobalISelAbort = GlobalISelAbort, - .DebugMachineScheduler = DebugMachineScheduler}); + .DebugMachineScheduler = DebugMachineScheduler, + .DebugPrologueEpilogue = DebugPrologueEpilogue}); if (!Added) return std::unexpected(Added.error()); } else { @@ -152,7 +154,8 @@ createPasses(const MachineFunction &Function, const BackendInvocation &Invocatio riscv::RISCVPipelineOptions{.Optimization = Invocation.Optimization, .UseTargetCopyInstructions = UseTargetCopyInstructions, .GlobalISelAbort = GlobalISelAbort, - .DebugMachineScheduler = DebugMachineScheduler}); + .DebugMachineScheduler = DebugMachineScheduler, + .DebugPrologueEpilogue = DebugPrologueEpilogue}); if (!Pass) return std::unexpected(Pass.error()); auto Added = Pipeline.addPass(std::move(*Pass)); -- cgit v1.2.3