From e16de95dce32f077361577377d5c52fc4ad78339 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Fri, 7 Aug 2026 02:15:09 +0800 Subject: [RISCV] Add generated RV64GC register description Add an RCC-owned build-time target description generator and the initial RV64GC register model. Keep ABI aliases separate from canonical MIR register spelling. --- backend/unittests/CodeGen/TargetRegisterInfoTest.cpp | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'backend/unittests/CodeGen/TargetRegisterInfoTest.cpp') diff --git a/backend/unittests/CodeGen/TargetRegisterInfoTest.cpp b/backend/unittests/CodeGen/TargetRegisterInfoTest.cpp index da13e19..49f23c0 100644 --- a/backend/unittests/CodeGen/TargetRegisterInfoTest.cpp +++ b/backend/unittests/CodeGen/TargetRegisterInfoTest.cpp @@ -166,6 +166,19 @@ void testDescriptionRejection(TestContext &Context) { Context.expect(!rcc::TargetRegisterInfo::create(std::move(Description)), "duplicate register unit IDs must be rejected"); } + { + auto Description = rcc::test::createTestTargetRegisterInfoDescription(); + Description.PhysicalRegisters.front().AlternativeNames = {"later-name"}; + Description.PhysicalRegisters[1].Name = "later-name"; + Context.expect(!rcc::TargetRegisterInfo::create(std::move(Description)), + "canonical register names must not collide with earlier ABI aliases"); + } + { + auto Description = rcc::test::createTestTargetRegisterInfoDescription(); + Description.PhysicalRegisters.front().IsReserved = true; + Context.expect(!rcc::TargetRegisterInfo::create(std::move(Description)), + "statically reserved registers must not appear in allocation orders"); + } { auto Description = rcc::test::createTestTargetRegisterInfoDescription(); Description.PhysicalSubRegisters.front().SubReg = phys(rcc::test::TestRegister::G1Low32); -- cgit v1.2.3