From 9ae4dec7b8ce79587bde200fa8fadefe7f81d2bf Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 00:06:12 +0800 Subject: [MIR] Accept empty optional register fields --- backend/unittests/MIR/MIRDocumentTest.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'backend/unittests/MIR/MIRDocumentTest.cpp') diff --git a/backend/unittests/MIR/MIRDocumentTest.cpp b/backend/unittests/MIR/MIRDocumentTest.cpp index b6ca0bb..7192398 100644 --- a/backend/unittests/MIR/MIRDocumentTest.cpp +++ b/backend/unittests/MIR/MIRDocumentTest.cpp @@ -328,6 +328,7 @@ isSSA: true noVRegs: false registers: - { id: 7, class: gpr64, preferred-register: '$g1', flags: [ test-vreg-one ] } + - { id: 8, class: gpr64, preferred-register: '' } liveins: - { reg: '$g0', virtual-reg: '%7' } calleeSavedRegisters: [ '$g1' ] @@ -346,7 +347,7 @@ frameInfo: fixedStack: - { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8 } stack: - - { id: 4, name: slot, size: 8, alignment: 8, local-offset: 0, + - { id: 4, name: slot, size: 8, alignment: 8, callee-saved-register: '', local-offset: 0, debug-info-variable: '!0', debug-info-expression: '!DIExpression(DW_OP_LLVM_arg, 0, 18446744073709551615)', debug-info-location: '!DILocation(line: 4, column: 2, scope: !1, isImplicitCode: true)' } @@ -426,7 +427,7 @@ void testDocumentTransaction(TestContext &Context) { if (Function == nullptr) return; - Context.expect(Function->registerInfo().virtualRegisters().size() == 1 && + Context.expect(Function->registerInfo().virtualRegisters().size() == 2 && Function->registerInfo().liveIns().size() == 1 && Function->records().hasCalleeSavedRegisters(), "register tables must publish into the common MachineIR model"); -- cgit v1.2.3