From 379ff50dcc7ccf977379aee68fa9d10f69065d23 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 18:31:49 +0800
Subject: [MC] Implement RV64GC assembly emission

---
 backend/unittests/Target/Inputs/RISCVDataPipeline.mir | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 backend/unittests/Target/Inputs/RISCVDataPipeline.mir

(limited to 'backend/unittests/Target/Inputs/RISCVDataPipeline.mir')

diff --git a/backend/unittests/Target/Inputs/RISCVDataPipeline.mir b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir
new file mode 100644
index 0000000..f847640
--- /dev/null
+++ b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir
@@ -0,0 +1,18 @@
+---
+name: data_pipeline
+tracksRegLiveness: true
+isSSA: true
+constants:
+  - id: 0
+    value: 'i64 1234605616436508552'
+    alignment: 8
+jumpTable:
+  kind: block-address
+  entries:
+    - { id: 0, blocks: [ '%bb.0' ] }
+body: |
+  bb.0:
+    liveins: $x1
+    %0:gpr(i64) = G_CONSTANT 7
+    $x10 = COPY %0
+    PseudoRET implicit $x1, implicit $x10
-- 
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