From 379ff50dcc7ccf977379aee68fa9d10f69065d23 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 18:31:49 +0800
Subject: [MC] Implement RV64GC assembly emission

---
 backend/unittests/Target/Inputs/RISCVGenericPipeline.mir | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 backend/unittests/Target/Inputs/RISCVGenericPipeline.mir

(limited to 'backend/unittests/Target/Inputs/RISCVGenericPipeline.mir')

diff --git a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
new file mode 100644
index 0000000..d68cd72
--- /dev/null
+++ b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
@@ -0,0 +1,12 @@
+---
+name: generic_pipeline
+tracksRegLiveness: true
+isSSA: true
+body: |
+  bb.0:
+    liveins: $x1
+    %0:gpr(i64) = G_CONSTANT 42
+    %1:gpr(i64) = G_CONSTANT 1
+    %2:gpr(i64) = G_ADD %0, %1
+    $x10 = COPY %2
+    PseudoRET implicit $x1, implicit $x10
-- 
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