From 4fe5ee649927d54d6fb74904d7b97ad0f63fd587 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Tue, 11 Aug 2026 17:38:11 +0800
Subject: [RISCV] Legalize fixed-baseline RV64 MachineIR

---
 backend/unittests/Target/Inputs/RISCVGenericPipeline.mir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'backend/unittests/Target/Inputs/RISCVGenericPipeline.mir')

diff --git a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
index d68cd72..62c1baf 100644
--- a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
+++ b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir
@@ -5,8 +5,8 @@ isSSA: true
 body: |
   bb.0:
     liveins: $x1
-    %0:gpr(i64) = G_CONSTANT 42
-    %1:gpr(i64) = G_CONSTANT 1
-    %2:gpr(i64) = G_ADD %0, %1
+    %0:gprb(i64) = G_CONSTANT 42
+    %1:gprb(i64) = G_CONSTANT 1
+    %2:gprb(i64) = G_ADD %0, %1
     $x10 = COPY %2
     PseudoRET implicit $x1, implicit $x10
-- 
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