From 379ff50dcc7ccf977379aee68fa9d10f69065d23 Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 18:31:49 +0800
Subject: [MC] Implement RV64GC assembly emission

---
 backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir

(limited to 'backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir')

diff --git a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir
new file mode 100644
index 0000000..9695691
--- /dev/null
+++ b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir
@@ -0,0 +1,10 @@
+---
+name: wide_constant_pipeline
+tracksRegLiveness: true
+isSSA: true
+body: |
+  bb.0:
+    liveins: $x1
+    %0:gpr(i64) = G_CONSTANT 9223372036854775807
+    $x10 = COPY %0
+    PseudoRET implicit $x1, implicit $x10
-- 
cgit v1.2.3