From 3a57627e59ba18b6f9f9aae7bb60c390c0d3575a Mon Sep 17 00:00:00 2001
From: Richard-Qin-X <richard.qin.001@gmail.com>
Date: Sun, 9 Aug 2026 22:05:14 +0800
Subject: [MC] Implement RV64GC object emission

---
 backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir

(limited to 'backend/unittests/Target/Inputs')

diff --git a/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir
new file mode 100644
index 0000000..3105fe4
--- /dev/null
+++ b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir
@@ -0,0 +1,12 @@
+---
+name: stack_frame_pipeline
+tracksRegLiveness: true
+isSSA: true
+stack:
+  - { id: 0, size: 32, alignment: 16 }
+body: |
+  bb.0:
+    liveins: $x1
+    %0:gpr(i64) = G_CONSTANT 9
+    $x10 = COPY %0
+    PseudoRET implicit $x1, implicit $x10
-- 
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