From 4fe5ee649927d54d6fb74904d7b97ad0f63fd587 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 11 Aug 2026 17:38:11 +0800 Subject: [RISCV] Legalize fixed-baseline RV64 MachineIR --- backend/unittests/Target/Inputs/RISCVDataPipeline.mir | 2 +- backend/unittests/Target/Inputs/RISCVGenericPipeline.mir | 6 +++--- backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir | 2 +- backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'backend/unittests/Target/Inputs') diff --git a/backend/unittests/Target/Inputs/RISCVDataPipeline.mir b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir index f847640..0d0c35d 100644 --- a/backend/unittests/Target/Inputs/RISCVDataPipeline.mir +++ b/backend/unittests/Target/Inputs/RISCVDataPipeline.mir @@ -13,6 +13,6 @@ jumpTable: body: | bb.0: liveins: $x1 - %0:gpr(i64) = G_CONSTANT 7 + %0:gprb(i64) = G_CONSTANT 7 $x10 = COPY %0 PseudoRET implicit $x1, implicit $x10 diff --git a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir index d68cd72..62c1baf 100644 --- a/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir +++ b/backend/unittests/Target/Inputs/RISCVGenericPipeline.mir @@ -5,8 +5,8 @@ isSSA: true body: | bb.0: liveins: $x1 - %0:gpr(i64) = G_CONSTANT 42 - %1:gpr(i64) = G_CONSTANT 1 - %2:gpr(i64) = G_ADD %0, %1 + %0:gprb(i64) = G_CONSTANT 42 + %1:gprb(i64) = G_CONSTANT 1 + %2:gprb(i64) = G_ADD %0, %1 $x10 = COPY %2 PseudoRET implicit $x1, implicit $x10 diff --git a/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir index 3105fe4..4f37d15 100644 --- a/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir +++ b/backend/unittests/Target/Inputs/RISCVStackFramePipeline.mir @@ -7,6 +7,6 @@ stack: body: | bb.0: liveins: $x1 - %0:gpr(i64) = G_CONSTANT 9 + %0:gprb(i64) = G_CONSTANT 9 $x10 = COPY %0 PseudoRET implicit $x1, implicit $x10 diff --git a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir index 9695691..1b9ee82 100644 --- a/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir +++ b/backend/unittests/Target/Inputs/RISCVWideConstantPipeline.mir @@ -5,6 +5,6 @@ isSSA: true body: | bb.0: liveins: $x1 - %0:gpr(i64) = G_CONSTANT 9223372036854775807 + %0:gprb(i64) = G_CONSTANT 9223372036854775807 $x10 = COPY %0 PseudoRET implicit $x1, implicit $x10 -- cgit v1.2.3