From e6cd1347cc2c76babe56842e1b7bd05d68fe9584 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Tue, 11 Aug 2026 23:44:57 +0800 Subject: [RISCV] Model typed floating-point register views --- backend/unittests/Target/RISCVCallLoweringTest.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'backend/unittests/Target/RISCVCallLoweringTest.cpp') diff --git a/backend/unittests/Target/RISCVCallLoweringTest.cpp b/backend/unittests/Target/RISCVCallLoweringTest.cpp index c18898f..33723b1 100644 --- a/backend/unittests/Target/RISCVCallLoweringTest.cpp +++ b/backend/unittests/Target/RISCVCallLoweringTest.cpp @@ -226,6 +226,17 @@ void testIntegerAndFloatingAssignments(TestContext &Context) { FloatAssignments[16].StackOffsetBytes == 0, "LP64D floating arguments must fall back from fa0-fa7 to a0-a7 and then stack"); + auto Single = callRequest({abiValue(floating(rcc::FloatSemantics::IEEESingle), 0)}, 1); + Single.Results = {abiValue(floating(rcc::FloatSemantics::IEEESingle), 0)}; + auto SinglePlan = rcc::riscv::callLowering().planCall(Single); + Context.expect(SinglePlan && SinglePlan->argumentAssignments().size() == 1 && + SinglePlan->returnAssignments().size() == 1 && + isLocation(SinglePlan->argumentAssignments()[0], + physical(rcc::riscv::PhysicalRegisterID::F10_F)) && + isLocation(SinglePlan->returnAssignments()[0], + physical(rcc::riscv::PhysicalRegisterID::F10_F)), + "LP64D f32 arguments and returns must use the FPR32 physical-register view"); + auto FloatFragment = abiValue(floating(rcc::FloatSemantics::IEEEDouble), 0); FloatFragment.FragmentCount = 2; FloatFragment.OriginalAlignment = align(16); -- cgit v1.2.3