From d91d57297bdb30b6363e259ab75d517dc333e292 Mon Sep 17 00:00:00 2001 From: Richard-Qin-X Date: Wed, 12 Aug 2026 00:26:10 +0800 Subject: [RISCV] Support absolute address operand flags --- backend/unittests/Target/RISCVTargetTest.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'backend/unittests/Target/RISCVTargetTest.cpp') diff --git a/backend/unittests/Target/RISCVTargetTest.cpp b/backend/unittests/Target/RISCVTargetTest.cpp index 2d1be09..2077496 100644 --- a/backend/unittests/Target/RISCVTargetTest.cpp +++ b/backend/unittests/Target/RISCVTargetTest.cpp @@ -119,9 +119,11 @@ void testABIAndDebugFacts(TestContext &Context) { TextLP64DMask != nullptr && LP64DMask != nullptr && *TextLP64DMask == *LP64DMask, "RV64GC must expose named LP64 and LP64D call-preserved masks"); - Context.expect(MIRText->directOperandFlagMask() == 31 && - MIRText->directOperandFlag("riscv-call") == 1, - "RV64GC MIR target flags must expose the canonical direct-call spelling"); + Context.expect(MIRText->directOperandFlagMask() == 127 && + MIRText->directOperandFlag("riscv-call") == 1 && + MIRText->directOperandFlag("riscv-hi") == 32 && + MIRText->directOperandFlag("riscv-lo") == 64, + "RV64GC MIR target flags must expose canonical call and address spellings"); Context.expect(MIRText->dwarfRegister(X1) == 1, "the return-address register must retain its DWARF register number"); Context.expect(MIRText->dwarfRegister(F31D) == 63 && MIRText->dwarfRegister(F31F) == 63 && -- cgit v1.2.3